NetNews Offline 2/NetNews Offline Volume 2.iso/news/comp/sys/amiga/programmer/1316

Internet Message Format | 1996-08-05 | 3.4 KB

Path: informatik.tu-muenchen.de!fischerj
From: [e-mail] (Juergen "Rally" Fischer)
Newsgroups: comp.sys.amiga.programmer
Subject: Re: TMapping again!
Date: 17 Jan 1996 19:34:53 GMT
Organization: Technische Universitaet Muenchen, Germany
Distribution: world
Message-ID: <4djj0t$[e-mail]>
References: <4d0ou6$[e-mail]> <Z31Wx*[e-mail]> <4d42di$[e-mail]> <4d5lvi$[e-mail]> <4d6v0t$[e-mail]>
NNTP-Posting-Host: hphalle5.informatik.tu-muenchen.de
Originator: [e-mail]



In article <4d6v0t$[e-mail]>, [e-mail] (Stephan Schaem) writes:
|> Organization: Teleport - Portland's Public Access [phone]
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|> References: <4d0ou6$[e-mail]> <Z31Wx*[e-mail]> <4d42di$[e-mail]> <4d5lvi$[e-mail]>
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|> Philipp Boerker ([e-mail]) wrote:
|> : [e-mail] (Stephan Schaem) writes:
|>
|> : >Andre Weissflog ([e-mail]) wrote:
|> : >: In article <4d0ou6$[e-mail]>, Lasse Staff Jensen writes:
|>

|>
|>  AAAAAA..........BBBBBCCCCCCDDDDD
|>
|>  A = x fraction
|>  B = y integer
|>  C = y fraction
|>  D = x integer
|>  . = zero or more precision for x
|>
|>  Has you see the example above work...

uhm has anyone actually seen the mapper work ? IMHO the fact that
CCCCCC y fraction also causes an adress, this could be used imho
for smoother mapping!

I guess you normally use 32 equal pixels, but if you'd use 32 values
beeing interpolated between 2 pix of the "real 32x32 map", then it
should give you interpolation for free!

maybe a outzoomed polygon looks better with it.

|> : Yes, I agree. Sharon, one of the coders of matrix, is actually a
|> : PC coder but his polygon engine on a 33 MHz 486 is slower than
|> : our (Sharon, Grond, Skyphos all/matrix) engine on a 25 MHz 030!
|> : And think of not having chunky screens, not having L2 cache,
|> : not having 8kb L1 cache...
|> : That's the power of a large register set!

well is you polyengine still faster using 8 planes ? ;)
he got a non-local-bus vga ? ;)

It depends on the routine if a large register set is needed.
inner loops can live with x86 chipset, but when it comes to
2st outer, the L1 caches have to play the role of a larger
register set.

my friend always agures that you could see the cache as big register
set on intel, but I disagree, a mapper loads so much from mem that
your variables in cache are bombed by the texture data (and afaik
even instruction code is bombed by it as there is AFAIK no separate
instruction cache on 486).

|>
|>  The x86 design is just crap... it would still be crap with more register :)

heehee ;)

|>
|> : Gee, how am I waiting for the 32 regs of the PPC... 8)
|>
|>  Well, you are trading your nice addressing mode for this,
|>  no more (offset,base,offset*scale) ;) You will probably need
|>  an extra register and 3 instruction to emulate this on a ppc.
argh ?

|>  And not all 32 register are for you to play with ... dont know
|>  the PPC so I wont go into details :)
|>
|>  Stephan
|>
|>
------------------------------------------------------------------------
   [e-mail] (Juergen "Rally" Fischer)   =:)